1. Field of the Invention
The present invention relates to super high voltage semiconductor devices and, more particularly, to a high voltage metal-oxide-semiconductor (HV MOS) transistor device having a structure of a combination of trench and field plate structures.
2. Description of the Prior Art
In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral diffused MOS (LDMOS), is employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages. LDMOS transistors are particularly prevalent because they can operate with a high efficiency and their planar structure allows for easy integration on a semiconductor die with other circuitry.
For the structure of a conventional HV LDMOS transistor device, a field oxide region with a long lateral width is positioned between the gate and drain to increase the breakdown voltage and prevent the high voltage device from breaking down. While, to achieve a good improvement of the breakdown voltage, a certain width is needed for the field oxide region and the resulting size of the device is relatively large.
In order to reduce the size at the same performance, it is known that a plurality of field plates is formed to be arranged on the field oxide region. FIG. 1 schematically illustrates a cross-sectional view of a conventional super high voltage NMOS transistor device. The conventional super high voltage NMOS transistor device 1 is fabricated on an active area of a semiconductor substrate 10 such as a P type silicon substrate. The active area is isolated with a peripheral field oxide region. Generally, the conventional super high voltage NMOS transistor device 1 comprises a source diffusion region 12, a gate 14 and a drain diffusion region 16. The source diffusion region 12 is a heavily N doped region bordering upon a heavily P doped region 18, both of which are formed within a P-type well 20. The distance between the drain diffusion region 16 and the source diffusion region 12 may be a few micrometers. The drain diffusion region 16 is a heavily N doped drain and is formed within an N-type well 22 that is formed within a deep N-type well 24, forming a triple-well structure.
As shown in FIG. 1, a gate dielectric layer 26 is formed on the source diffusion region 12. The gate 14 is formed on the gate dielectric layer 26 and laterally extends over a field oxide layer 28. The field oxide layer 28 is formed between the source diffusion region 12 and drain diffusion region 16 using a local oxidation of silicon (LOCOS) technique. Furthermore, a plurality of floating field plates 30 is formed on the field oxide layer 28 to disturb the lateral electric field. Accordingly, the size of the conventional super high voltage NMOS transistor device 1 has a smaller size than that of the conventional super high voltage NMOS transistor without field plates.
However, there is still a need for an improved HV MOS structure and the manufacturing method to reduce the size or to improve breakdown voltage of the HV MOS transistor device.